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RT8800/B
General Purpose 2/3-Phase PWM Controller for High-Density Power Supply
General Description
The RT8800/B are general purpose multi-phase synchronous buck controllers dedicating for high density power supply regulation. The parts implement 2, and 3 buck switching stages operating in interleaved phase set automatically. The output voltage is regulated and controlled following the input voltage of FB pin. With such a single analog control, the RT8800/B provide a simple, flexible, wide-range and extreme cost-effective highdensity voltage regulation solutions for various high-density power supply application. The RT8800/B multi-phase architecture provide high output current while maintaining low power dissipation on power devices and low stress on input and output capacitors. The high equivalent operating frequency also reduces the component dimension and the output voltage ripple in load transient. RT8800/B implement both voltage and current loops to achieve good regulation, response and power stage thermal balance. The RT8800/B apply the time sharing DCR current sensing technology newly as well; with such a topology, the RT8800/B extract the DCR of output inductor as sense component to deliver a more precise load line regulation and better thermal balance capability. Moreover, the parts monitor the output voltage for overcurrent and over-voltage protection; Soft-start and programmable under-voltage lockout are also provided to assure the safety of power system.
Features
5V Power Supply Voltage 2/3-Phase Power Conversion with Automatic Phase Selection (RT8800 : 2/3-Phase, RT8800B : 2-Phase) Output Voltage Controlled by External Reference Voltage Precise Core Voltage Regulation Power Stage Thermal Balance by DCR Current Sensing Extreme Low-Cost, Lossless Time Sharing Current Sensing Internal Soft-start Hiccup Mode Over-Current Protection Over-Voltage Protection Adjustable Operating Frequency and Typical at 300kHz Per Phase Power Good indication Small 16-Lead VQFN Package (For RT8800 only) RoHS Compliant and 100% Lead (Pb)-Free
Ordering Information
RT8800/B Package Type QV : VQFN-16L 3x3 (V-Type) S : SOP-16 Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commercial Standard) 2-Phase 2/3-Phase
Applications
Desktop CPU core power Low Output Voltage, High power density DC-DC Converters Voltage Regulator Modules
Note :
RichTek Pb-free and Green products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. 100% matte tin (Sn) plating.
Marking Information
For marking information, contact our sales representative directly or through a RichTek distributor located in your area, otherwise visit our website for detail.
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RT8800/B
Pin Configurations
(TOP VIEW)
PWM3 PWM2 PWM1 VDD
16 15 14 13
DACFB 1 DACQ 2 FB 3 DVD 4
5
12 ISP1
GND
11 ISP2 10 ISP3 9
PGOOD
6
7
8
COMP
ICOMMON
VDD DACFB DACQ FB DVD COMP PI RT
2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
PWM2 PWM1 N/C
ISP1 ISP2
PGOOD GND ICOMMON
PI
RT
SOP-16 RT8800B
VQFN-16L 3x3 RT8800
Functional Pin Description
DACFB Negative input of internal buffer amplifier for reference voltage regulation. The pin voltage is locked at internal VREF = 0.8V by properly close the buffer amplifier feedback loop. DACQ The pin is defined as the output of internal buffer amplifier for reference voltage regulation. FB The pin is defined as the inverting input of internal error amplifier. DVD The pin is defined as a programmable power UVLO detection input. Trip threshold = 0.8V at VDVD rising. COMP The pin is defined as the output of the error amplifier and the input of all PWM comparators. PI The pin is defined as the positive input of the error amplifier. RT Switching frequency setting. Connect this pin to GND with a resistor to set the frequency.
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ICOMMON Common negative input of current sense amplifiers for all three channels. PGOOD Output power-good indication. The signal is implemented as an output signal with open-drain type. ISP1 , ISP2 , ISP3 Current sense positive inputs for individual converter channel current sense. PWM1 , PWM2 , PWM3 PWM outputs for each phase switching drive. VDD Chip power supply. Connect this pin to a 5V supply. GND Chip power ground. Exposed Pad (RT8800) Exposed pad should be soldered to PCB board and connected to GND.
Typical Application Circuit
DS8800/B-06 March 2007
D1 SS12/SM 12V C7 1uF R20 10 C9 1uF C12 1uF C11 2200uF Q1 5V L1 C13 1uH 1000uF 12V
C1 33pF
Optional for R&C
14 VDD PVCC UGATE1 PHASE1
Q2 R25 2.2 PHASE1 C14 3.3nF C4 C8 1uF
11 BOOT1 12 13
R22 0 Q3
PHB95N03LT PHB83N03LT
R2
C3 R16 0
5
R21 0
R1 15k
C2 10nF
R3 3k
1 PWM1 RT9602 4
L2 0.5uH VCORE
6 1 FB
4
VDD
15 PWM1
COMP
VID5
R4 110k
R5 56k
RDROOP PWM2 GND 10 3 GND PHASE2 LGATE2 7
PHB83N03LT
7 PWM2 UGATE2 8 9
R23 0
(Note : The inductor' s DCR value must be large than 0.3m
VID0
PI
16
R17 0
LGATE1 2
R6 27k
VID1
VID2
R7 13k
R11 1.8k
3 DACQ
RT8800B 12 6 PGND
R18 PHASE2 R
2 DACFB ISP2
ISP1
C15 2200uF
C16 1uF C18 to C29 1000uF x 12 Q4 PHASE2 L3 0.5uH C30 to C33 10uF x 4
VID3
R8 6.8k
11
ICOMMON
VID4
R9 3.3k
R12 10k
PGOOD
3.3V
DVD 5
RT 8
R10 5.1k
13
Optional C5 1uF Optional 430 RICOMMON1 C6 1uF VCORE R R19 PHASE1 D2 SS12/SM
9
Figure A. 2-phase with resistive DAC
BOOT2 10
C10 1uF R24 0
PHB95N03LT
12V R15 16k
Q5 Q6
R13 27k R14 3k
R26 2.2 C17 3.3nF
: X7R/R-type capacitor is required for all time constant setting capacitor of DCR sensing.)
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Optional
RICOMMON2
RT8800/B
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PVCC2
PHASE2
LGATE2
16 BOOT2 RT9605 PVCC3 GND PHASE3 15 11 12V PWM3 PWM2 PWM1 BOOT1 LGATE3 7 15 5 4
R16 PHASE3 R
UGATE2
R1 15k
C3 10nF
R3 3k
NC
PHASE1
PVCC1
LGATE1
ICOMMON
DVD 4
RT 7
Figure B. 3-phase with resistive DAC
C15 R18 0 12V 1uF R20 0 5V C4 4.7uF C10 to C13 1500uF x 4 C14 1uF
R10 5.1k
3.3V
12
R13 R15 16k Optional 430 Optional C7 1uF VCORE RICOMMON1 R R17 PHASE1 D2 Q4 12V VIN C6 1uF R C17 1uF R21 0
27k
Optional
R17 PHASE2
1
UGATE1
24
22
12V
23
C18 1uF
8 R23 10
R22 0 C19 1uF
VDD
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PHASE2 L1 0.5uH 12V VIN Q3 Q1 D1 Q2 1uH C8 1000uF C9 1uF R19 2.2 C16 3.3uF C24 to C35 1000uF x 12
RT8800/B
C1 33pF
Optional C2 R2
17
19
21 20 3
Q7 PHASE3 C23 3.3nF Q8 C21 1uF R27 2.2 R26 0 L2 0.5uH
R25 14 0
C36 to C39 10uF x 4
16
5 FB
3
VDD
R4 110k
13 PWM1
COMP
VID5
RDROOP
VID0
R5
56k
R6
27k
6 PI 2 DACQ RT8800 GND ISP3 2 ISP2
C5 1uF
PWM3 PWM2 10 11 Optional 14
VCORE Q9
VID1
R7
13k
R11 1.8k
UGATE3 10 BOOT3 9
C22 1uF
VID2
1 DACFB
D3
VID3
R8 6.8k
9 ISP1
PGOOD
VID4
R9 3.3k
R12 10k
12V
VIN
8
12V
5VSB PHASE1 L3 0.5uH Q5 R24 2.2 C20 3.3nF Q6
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R14 3k
RICOMMON2
DS8800/B-06 March 2007
PHASE2 L1 0.5uH 12V VIN Q3 Q1 Q2 C17 C11 to C14 1500uF x 4 C15 1uF R13 0 12V 1uF R15 0 C25 to C36 1000uF x 12 D1 1uH C9 1000uF C10 1uF 5V C5 4.7uF R14 2.2 C16 3.3uF
PVCC2
UGATE2
PHASE2
LGATE2 NC
PHASE1
PVCC1
LGATE1
ICOMMON
3.3V
DVD 4
RT 7
R7 27k
R8 3k Optional 430 Optional C8 1uF VCORE RICOMMON1 R Q4 12V VIN R12 PHASE1 D2 R9 16k C7 1uF R C18 1uF R16 0 12V
Optional
R11 PHASE2
1
UGATE1
24
22
23
C19 1uF
8 R19 10
R18 0 C20 1uF
VDD
DS8800/B-06 March 2007
17 19 21 20 3
Q7 PHASE3 C24 3.3nF Q8 C22 1uF R22 2.2 R21 0 L2 0.5uH VCORE Q9
C1 33pF
Optional C3 R2
R1 15k
C2 10nF
R3 3k
16
5 16 BOOT2 RT9605 PVCC3 GND PHASE3 UGATE3 10 BOOT3 9
C23 1uF
3 LGATE3 15 11 12V 14 FB 7 PWM3 PWM2 PWM1 BOOT1 15 5 4
R10 Optional PHASE3 R C6 1uF
R20 0
C37 to C40 10uF x 4
VDD
13 PWM1
COMP
RDROOP
6 RT8800 GND ISP3 2 ISP2 ISP1 11 10 PWM2 14 PWM3
C4 10nF
PI 2 DACQ
R4 5.1k
1 DACFB
R5 5.1k
9
PGOOD
R6 10k
12V
VIN
12
8
12V
5VSB
PHASE1
RT9401A/B
Figure C. 3-phase with RT9401A/B DAC generator
L3 0.5uH Q5 R17 2.2 C21 3.3nF Q6
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1
VID2
VID3
8
2
VID1
VID4
7
RICOMMON2
3
VDA
GND
6
RT8800/B
5V
4
VDD
VID0
5
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Oscillator & Ramp Generator PWM Logic & Driver PWM1 + + PWMCP INH PWM Logic & Driver PWM2 + + + +
+ + PWMCP EA + -
OVP OCP Sample & Hold MAJ SUM/N & OCP Detection Sample & Hold Sample & Hold Mux
Mux
500mV + Buffer Amplifier
0.8V VREF
DACQ
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Power On Reset Soft Start + + PWMCP INH PWM Logic & Driver PWM3 + + GND + GM ICOMMON
ISP1 ISP2 ISP3
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PGOOD VDD DVD RT INH
RT8800/B
Function Block Diagram
COMP
FB PI
DACFB
DS8800/B-06 March 2007
RT8800/B
Table. Output Voltage Program
VID5 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 VID3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 VID2 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 VID1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 VID0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 Nominal Output Voltage (V) 1.0800 1.1000 1.1125 1.1250 1.1375 1.1500 1.1625 1.1750 1.1875 1.2000 1.2125 1.2250 1.2375 1.2500 1.2625 1.2750 1.2875 1.3000 1.3125 1.3250 1.3375 1.3500 1.3625 1.3750 1.3875 1.4000 1.4125 1.4250 1.4375 1.4500 1.4625 1.4750 1.4875 1.5000 1.5125 1.5250 1.5375 1.5500
To be continued
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RT8800/B
Table. Output Voltage Program
VID5 0 1 0 1 1 1 1 1 1 1 1 1 1 1
Note: 1 : Open 0 : VSS or GND
VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0
VID3 1 1 1 1 1 1 0 0 0 0 0 0 0 0
VID2 1 0 0 0 0 0 1 1 1 1 0 0 0 0
VID1 0 1 1 1 0 0 1 1 0 0 1 1 0 0
VID0 0 1 1 0 1 0 1 0 1 0 1 0 1 0
Nominal Output Voltage (V) 1.5625 1.5750 1.5875 1.6000 1.6250 1.6500 1.6750 1.7000 1.7250 1.7500 1.7750 1.8000 1.8250 1.8500
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RT8800/B
Absolute Maximum Ratings
(Note 1) Supply Voltage, VDD ------------------------------------------------------------------------------------------- 7V Input, Output or I/O Voltage ---------------------------------------------------------------------------------- GND - 0.3V to VDD + 0.3V Power Dissipation, PD @ TA = 25C VQFN-16L 3X3 -------------------------------------------------------------------------------------------------SOP-16 ----------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 4) VQFN-16L 3X3, JA --------------------------------------------------------------------------------------------SOP-16, JA ----------------------------------------------------------------------------------------------------Junction Temperature -----------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------------ESD Susceptibility (Note 2) HBM (Human Body Mode) ----------------------------------------------------------------------------------MM (Machine Mode) ------------------------------------------------------------------------------------------1.47W 1W 68C/W 100C/W 150C 260C -65C to 150C 2kV 200V
Recommended Operating Conditions
(Note 3)
Supply Voltage, VDD ------------------------------------------------------------------------------------------- 5V 10% Ambient Temperature Range --------------------------------------------------------------------------------- 0C to 70C Junction Temperature Range --------------------------------------------------------------------------------- 0C to 125C
Electrical Characteristics
(VDD = 5V, TA = 25C, unless otherwise specified)
Parameter VDD Supply Current Nominal Supply Current Power-On Reset Rising VDD Threshold Hysteresis 4.0 0.2 0.75 -4.2 0.5 0.8 65 4.5 -0.85 -V V V mV IDD PWM 1,2,3 Open -5 -mA Symbol Test Conditions Min Typ Max Units
DVD Rising Threshold DVD Hysteresis Oscillator Free Running Frequency Frequency Adjustable Range Ramp Amplitude Ramp Valley Maximum On-Time of Each Channel Minimum On-Time of Each Channel RT Pin Voltage VRT RRT = 16k fOSC fOSC_ADJ VOSC VRV RRT = 16k RRT = 16k
170 50 --62 -0.77
200 -1.7 1.0 66 120 0.82
230 400 --75 -0.87
kHz kHz V V % ns V
To be continued
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RT8800/B
Parameter Reference Voltage Reference Voltage DACFB Sourcing Capability Error Amplifier DC Gain Gain-Bandwidth Product Slew Rate Current Sense GM Amplifier Recommended Full Scale Source Current OCP trip level Protection Over-Voltage Trip (VFB - VDACQ) Power Good PGOOD Output Low Voltage PGOOD Delay VPGOOD IPGOOD = 4mA -4 --0.2 8 V ms -500 -mV IOCP -160 100 190 -220 A A GBW SR CL = 10pF CL = 10pF ---65 10 8 ---dB MHz V/s VDACFB 0.79 -0.8 -0.81 10 V mA Symbol Test Conditions Min Typ Max Units
TPGOOD_Delay 90% * VOUT to PGOOD_H
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution recommended. Note 3. The device is not guaranteed to function outside its operating conditions. Note 4. JA is measured in the natural convection at T A = 25C on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard.
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RT8800/B
Typical Operating Characteristics
Load Line
1.4 1.38
Efficiency vs. Output Current
100 90 80
RLL = 1.5m, RICOMMON2 = 10k, RDROOP = 100 VIN = 12V
VIN = 12V, VOUT = 1.4V
Output Voltage (V)
1.36 1.34 1.32 1.3 1.28 1.26 1.24 0 10 20 30 40 50 60 70 80 90 100
Efficiency (%)
70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100
Driver RT9605
Output Current (A)
Output Current (A)
Frequency vs. RRT
1000 900 800
GM
90 80 70 60
RICOMMON1 = 430
Frequency (kHz)
700
I ADJ (uA)
600 500 400 300 200 100 0 0 5 10 15 20 25 30 35 40 45 50 55 60
50 40 30 20 10 0 0 10 20 30 40 50 60 70 80
GM3 GM2 GM1
90 100 110
RRT (k ) (k)
VC (mV)
VREF vs. Temperature
0.815 0.81 0.805
OCP Trip Point vs. Temperature
240 210 180 150
V REF (V)
Ix (uA)
-25 -10 5 20 35 50 65 80 95 110 125
0.8 0.795 0.79 0.785 0.78
120 90 60 30 0 -25 -10 5 20 35 50 65 80 95
Temperature (C)
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Temperature (C)
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RT8800/B
Frequency vs. Temperature
350 300
Load Transient Response
V CORE (200mV/Div)
Frequency (kHz)
250 200 150 100 50
UGATE1 (20V/Div) UGATE2 (20V/Div) UGATE3 (20V/Div)
phase 1, IOUT = 5A to 85A @SR = 93A/us)
RRT = 16k
0 -25 -10 5 20 35 50 65 80 95 110 125
Time (2.5s/Div)
Temperature (C)
Load Transient Response
V CORE (200mV/Div) V CORE (200mV/Div)
Load Transient Response
UGATE1 (20V/Div) UGATE2 (20V/Div) UGATE3 (20V/Div)
phase2, IOUT = 5A to 85A @SR = 93A/us)
UGATE1 (20V/Div) UGATE2 (20V/Div) UGATE3 (20V/Div)
phase 3, IOUT = 5A to 85A @SR = 93A/us)
Time (2.5s/Div)
Time (2.5s/Div)
Over Current Protection
Short While Turn_On
Over Current Protection
Short After Turn_On
IL1+IL2 (50A/Div) IL1+IL2 (50A/Div) V CORE (1V/Div) PWM1 (10V/Div) VCOMP (2V/Div) Time (10ms/Div) V CORE (1V/Div) PWM1 (10V/Div) VCOMP (2V/Div) Time (10ms/Div)
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RT8800/B
VID On the Fly Falling
IOUT = 5A
VID On the Fly Falling
V CORE (50mV/Div) PWM (5V/Div) VFB (200mV/Div)
IOUT = 90A
PWM (5V/Div) V CORE (100mV/Div) VFB (200mV/Div)
VID0 (2V/Div)
VID0 (2V/Div)
Time (25s/Div)
Time (25s/Div)
VID On the Fly Rising
IOUT = 5A
VID On the Fly Rising
IOUT = 90A
PWM (5V/Div)
PWM (5V/Div)
V CORE (200mV/Div) VFB (200mV/Div) VID0 (2V/Div) Time (10s/Div)
V CORE (200mV/Div) VFB (200mV/Div) VID0 (2V/Div) Time (10s/Div)
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RT8800/B
Application Information
RT8800/B are multiphase DC/DC controllers for extreme low cost applications that precisely regulate CPU core voltage and balance the current of different power channels using time sharing current sensing method. The converter consisting of RT8800/B and its companion MOSFET driver RT96xx series provide high quality CPU power and all protection functions to meet the requirement of modern VRM. Phase Setting and Converter Start Up RT8800/B interface with companion MOSFET drivers (like RT9602, RT9603, and RT9605) for correct converter initialization. RT8800/B will sense the voltage on PWM pins at the instant of POR rising. If the voltage is smaller than (VDD - 1.2V) the related channel is activated. Tie the PWM to VDD and the corresponding current sense pins to GND or left float if the channel is unused. For example, for 2-Channel application, tie PWM3 to VDD and ISP3 to GND (or let ISP3 open). PGOOD Function and Soft Start To indicate the condition of multiphase converter, RT8800/B provide PGOOD signal through an open drain connection. The output becomes high impedance after internal SS ramp > 3.5V. duty width according to its magnitude above the ramp signal. The output follows the ramp signal, SS. However while VOUT increases, the difference between VOUT and SSE(SS - V GS) is reduced and COMP leaves the saturation and declines. The takeover of SS lasts until it meets the COMP. During this interval, since the feedback path is broken, the converter is operated in the open loop. 3) Mode3 ( Cross-over< SS < VGS + VREF) When the Comp takes over the non-inverting input for PWM Amplifier and when SSE (SS - VGS) < VREF, the output of the converter follows the ramp input, SSE (SS - VGS). Before the crossover, the output follows SS signal. And when Comp takes over SS, the output is expected to follow SSE (SS - VGS). Therefore the deviation of VGS is represented as the falling of VOUT for a short while. The COMP is observed to keep its decline when it passes the cross-over, which shortens the duty width and hence the falling of VOUT happens. Since there is a feedback loop for the error amplifier, the output' s response to the ramp input, SSE (SS - VGS) is lower than that in Mode 2. 4) Mode 4 (SS > VGS + VREF) When SS > VGS + VREF, the output of the converter follows the desired VREF signal and the soft start is completed now. Voltage Control
COMP VRAMP_Valley Cross-over SS_Internal V CORE SSE_Internal
1) Mode 1 (SS< Vramp_valley) Initially the COMP stays in the positive saturation. When SS< VRAMP_Valley, there is no non-inverting input available to produce duty width. So there is no PWM signal and VOUT is zero. 2) Mode 2 (VRAMP_Valley< SS< Cross-over) When SS>VRAMP_Valley, SS takes over the non-inverting input and produce the PWM signal and the increasing
The voltage control loop consists of error amplifier, multiphase pulse width modulator, driver and power components. As conventional voltage mode PWM controller, the output voltage is locked at the positive input of error amplifier and the error signal is used as the control signal of pulse width modulator. The PWM signals of different channels are generated by comparison of EA output and split-phase sawtooth wave. Power stage transforms VIN to output by PWM signal on-time ratio. Output Voltage Program The output voltage of a RT8800/B converter is programmed to discrete levels between 1.08V and 1.85V. The voltage identification (VID) pins program an external voltage reference (DACQ) with a 6-bit digital-to-analog converter (DAC). The level of DACQ also sets the OVP threshold. The output voltage should not be adjusted while the converter is delivering power. Remove input power before
DS8800/B-06 March 2007
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RT8800/B
changing the output voltage. Adjusting the output voltage during operation may trigger the over-voltage protection. The DAC function is a precision non-inverting summation amplifier shown in Figure 1. The resistor values shown are only approximations of the actual precision values used. Grounding any combination of the VID pins increases the DACQ voltage. The "open" circuit voltage on the VID pins is the band gap reference voltage (VREF = 0.8V).
VCORE vs. Temperature
1.38 1.375 1.37
CPU : P4-2.8G VCORE = 1.35V
R = 1/3
V CORE (V)
1.365 1.36 1.355 1.35 1.345
R = 1/9
VID0 VID1 VID2 VID3 VID4 VID5
R R R R R R
VREF (0.8V) VDACFB
1.34
The Original R
+ OP RF
VDACQ
1.335 30 35 40 45 50 55 60 65 70
Temperature (C)
Figure 3
RG
VCORE vs. Temperature
1.66 1.64 1.62
Figure 1. The Structure of Discrete DAC Generator DAC Design Guideline In high temperature environment, V CORE becomes unstable for the leakage current in VID pins is increasing. The leakage will increase current consumption of CPU, and then raise RT8800's VDACQ reference output, so does VCORE voltage. Below are four comparison charts for different CPUs.
Note: In Below Figure 2 to Figure 5, The Original R means the resister values shown in typical application circuit. R=1/3 and R=1/9 mean that The Original R is divided by 3 or 9.
CPU : Celeron 2.0G VCORE = 1.55V
The Original R
V CORE (V)
1.6
R = 1/3
1.58 1.56 1.54 1.52 30 35 40 45 50 55 60 65 70
R = 1/9
Temperature (C)
Figure 4
VCORE vs. Temperature
1.68 1.66 1.64
VCORE vs. Temperature
1.64 1.63 1.62
CPU : P4-3.06G VCORE = 1.55V The Original R
CPU : P4-3.2G VCORE = 1.55V
The Original R
1.61
V CORE (V)
V CORE (V)
1.62 1.6 1.58
1.6 1.59 1.58 1.57
R = 1/3
R = 1/3
R = 1/9
1.56
1.56 1.55
R = 1/9
1.54 30 35 40 45 50 55 60 65 70
1.54 30 35 40 45 50 55 60 65 70
Temperature (C)
Temperature (C)
Figure 2
DS8800/B-06 March 2007
Figure 5
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RT8800/B
In order to maintain the VDACQ within 1% tolerance in the worst case, the total driver current of the DAC regulator should support up to 40mA. As the design of RT8800/B, the maximum driving current of the internal OP is 10mA. As shown in Figure 6, we suggest to add an external transistor 2N3904 for higher current for VDAC regulation.
VCC
for switching, period = TS VIN - VO VO - ( ) x TS DCR VIN IX(S/H) = IL(AVG) x 2L RICOMMON1
Falling Slope = Vo/L
IL IL(AVG)
VID0 VID1 VID2 VID3 VID4 VID5
1.34k 645 310 162 81 2.63k
VREF (0.8V) VDACFB
+ OP 43
VDACQ
Q1 2N3904 PI
Inductor Current
IL(S/H)
121
PWM Signal & High Side MOSFET Gate Signal
Figure 6. Immune circuit against CPU Leakage Current Current Sensing Setting RT8800/B senses the current flowing through inductor via its DCR for channel current balance and droop tuning. The differential sensing GM amplifier converts the voltage on the sense component (can be a sense resistor or the DCR of the inductor) to current signal into internal circuit (see Figure 7).
Low Side MOSFET Gate Signal
Figure 8. Inductor current and PWM signal Figure 9 is the test circuit for GM. We apply test signal at GM inputs and observe its signal process output by PI pin sinking current. Figure 10 shows the variation of signal processing of all channels. We observe zero offsets and good linearity between phases.
L VC = R x C VC = DCR x IL I X = DCR RICOMMON1
L IL R
+ -
DCR C +V C
L DCR C ESR +V C VISPX +V ICOMMON RICOMMON1 GMx 1k Ix
GMx Ix
RICOMMON
Figure 7. Current Sense Circuit The sensing circuit gets feedback. IX = IL x DCR RICOMMON1 by local
Figure 9. The Test Circuit of GM
IX is sampled and held just before low side MOSFET turns off (Figure 8).
IX(S/H) = IL(S/H) x DCR VO TOFF ; IL(S/H) = IL(AVG) x RICOMMON1 L 2 VIN - VO TOFF = ( ) x TS VIN
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RT8800/B
GM
70 60 50
GM3
I ADJ (uA)
GM2
40 30 20 10 0 0 20 40 60 80 100
For some case with preferable current ratio instead of current balance, the corresponding technique is provided. Due to different physical environment of each channel, it is necessary to slightly adjust current loading between channels. Figure 12. shows the application circuit of GM for current ratio requirement. Applying KVL along L+DCR branch and R1+C//R2 branch:
L dIL dVC VC + DCR x IL = R1 +C + VC dt dt R2
GM1
dVC R1 + R2 VC + dt R2 R2 For VC = DCR x IL R1 + R2 = R1 x C
VC (mV)
Look for its corresponding conditions:
L dIL dIL + DCR x IL = (R1//R2) x C x DCR x + DCR x IL dt dt L Let = (R1//R2) x C DCR Thus if L = (R1//R2) x C DCR R2 Then VC = x DCR x IL R1 + R2
Figure 10. The Linearity of GMx Figure 11 shows the time sharing technique of GM amplifier. We apply test signal at phase 3 and observe the waveforms at both pins of GM amplifier. The waveforms show time sharing mechanism and the perfomance of GM to hold both input pins equal when the shared time is on.
Time Sharing of GM
CH1:(2V/Div) CH2:(50mV/Div) CH3:(50mV/Div)
With internal current balance function, this phase would share (R 1+R 2)/R 2 times current than other phases. Figure 13 &14 show different settings for the power stages.
IL
PWM3
VISP3
1.5uH 1m
VISP3 and VICOMMON
VICOMMON
3k
1uF 3k
Time (1s/Div)
Figure 13. GM3 Setting for current ratio function
Figure 11 Current Ratio Setting
IL L DCR C R1 +V C R2
1.5k 1uF IL 1.5uH 1m
Figure 14. GM1,2 Setting for current ratio function
Figure 12. Application circuit for current ratio setting
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RT8800/B
L DCR C ESR
1.3
Load Line without dead zone at light loads
1.31
V CORE (V)
GMx Ix
V ISPX + V ICOMMON RICOMMON1 RICOMMON2
+V C
1.29 1.28 1.27 1.26
RICOMMOM2 open
RICOMMON2 = 82k
1.25
Figure 15. Application circuit of GM For load line design, with application circuit in Figure 15, it can eliminate the dead zone of load line at light loads. VISPX = VOUT +IL x DCR if GM holds input voltages equal, then VISPX = VICOMMON
IX = VICOMMON I x DCR +L RICOMMON2 RICOMMON1
1.24 1.23 0 5 10 15 20 25
I OUT (A)
Figure 16 Current Balance RT8800/B senses the inductor current via inductor' s DCR for channel current balance and droop tuning. The differential sensing GM amplifier converts the voltage on the sense component (can be a sense resistor or the DCR of the inductor) to current signal into internal balance circuit. The current balance circuit sums and averages the current signals and then produces the balancing signals injected to pulse width modulator. If the current of some power channel is larger than average, the balancing signal reduces that channels pulse width to keep current balance. The use of single GM amplifier via time sharing technique to sense all inductor currents can reduce the offset errors and linearity variation between GMs. Thus it can greatly improve signal processing especially when dealing with such small signal as voltage drop across DCR. Voltage Reference for Converter Output & Load Droop The positive input of error amplifier is PI pin that sinks current proportional to the sum of converter output current. VDRP = 2ISINK x RDRP. The load droop proportional to load current can be set by the resistor between PI pin & external VDACQ produced by either buffer amplifier or other voltage source. The PI pin voltage should be larger than 0.8V for good droop circuit performance.
=
VOUT + IL x DCR I x DCR +L RICOMMON2 RICOMMON1 VOUT RICOMMON2 + IL x DCR RICOMMON2 I x DCR +L RICOMMON1
=
For the lack of sinking capability of GM, RICOMMON2 should be small enough to compensate the negative inductor valley current especially at light loads.
VICOMMON I x DCR L RICOMMON2 RICOMMON1
Assume the negative inductor valley current is -5A at no load, then for RICOMMON1 = 330, RADJ = 160, VOUT = 1.300
- 5A x 1m 1.3V RICOMMON2 330
RICOMMON2 85.8k Choose RICOMMON2 = 82k
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RT8800/B
Over Current Protection
FB VDACQ PI + VDRP EA + ISINK 2xIX1 2xIX2 2xIX3
CH1:(5V/Div) CH2:(5V/Div)
PWM
Figure 17. Load Droop Circuit
DAC Offset Voltage Tuning The Intel specification requires that at no load the nominal output voltage of the regulator be offset to a value lower than the nominal voltage corresponding to the VID code. The offset is tuning from RG in the DAC generator as Figure 18.
VID0 VID1 VID2 VID3 VID4 VID5 R R R R R R RG VREF (0.8V) VDACFB
IL
Time (25ms/Div)
Figure 19. The Over Current Protection in the interval
+ OP RF
VDACQ
Over Current Protection
CH1:(5V/Div) CH2:(5V/Div)
PWM
Figure 18. The Structure of Discrete DAC Generator
If VID0~6 is set at VSS (Ground), and to suppose that shunt resistance is Rs. From below equation, we can tune the value of RG to increase or decrease the base voltage of VDACQ. VDACQ = (1 + RF RF ) x VREF + x VREF RG RS
VSS
Time (25ms/Div)
Figure 20. Over Current Protection at steady state
Over Current Protection OCP comparator co\mpares each inductor current sensed & sample/hold by current sense circuit with this reference current(150uA). RT8800/B uses hiccup mode to eliminate fault detection of OCP or reduce output current when output is shorted to ground.
Fault Detection The "hiccup mode" operation of over current protection is adopted to reduce the short circuit current. The in-rush current at the start up is suppressed by the soft start circuit through clamping the pulse width and output voltage by an internal slow rising ramp.
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RT8800/B
Design Procedure Suggestion a.Output filter pole and zero (Inductor, output capacitor value & ESR). b.Error amplifier compensation & sawtooth wave amplitude (compensation network). Current Loop Setting a.GM amplifier S/H current (current sense component DCR, ICOMMON pin external resistor value). b.Over-current protection trip point (RICOMMON1 resistor). VRM Load Line Setting a.Droop amplitude (PI pin resistor). b.No load offset (RICOMMON2) Power Sequence & SS DVD pin external resistor and SS pin capacitor. 2. Over-Current Protection Setting PCB Layout a.Sense for current sense GM amplifier input. b.Refer to layout guide for other items. Voltage Loop Setting Design Example Given: Apply for four phase converter VIN = 12V VCORE = 1.5V ILOAD(MAX) = 100A VDROOP = 100mV at full load (1m Load Line) OCP trip point set at 35A for each channel (S/H) DCR = 1m of inductor at 25C L = 1.5H COUT = 8000F with 5m equivalent ESR. 1. Compensation Setting a. Modulator Gain, Pole and Zero: From the following formula: Modulator Gain =VIN/VRAMP =12/2.4=5 (i.e 14dB) where VRAMP : ramp amplitude of saw-tooth wave
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RB1 4.7k
LC Filter Pole = 1.45kHz and ESR Zero =3.98kHz b. EA Compensation Network: Select R1 = 4.7k, R2 = 15k, C1 = 12nF, C2 = 68pF and use the Type 2 compensation scheme shown in Figure 21. By calculation, the F Z = 0.88kHz, FP = 322kHz and Middle Band Gain is 3.19 (i.e 10.07dB).
C2 68pF RB2 C1
15k 12nF EA +
Figure 21. Type 2 compensation network of EA
Consider the temperature coefficient of copper 3900ppm/C,
IL x DCR = 150 A RICOMMON1 IL x 1.39m = 150 A 330 IL = 35.6A
RT8800/B
Layout Guide
Place the high-power switching components first, and separate them from sensitive nodes. 1. Most critical path: The current sense circuit is the most sensitive part of the converter. The current sense resistors tied to ISP1,2,3 and ICOMMON should be located not more than 0.5 inch from the IC and away from the noise switching nodes. The PCB trace of sense nodes should be parallel and as short as possible. R&C filter of choke should place close to PWM and the R & C connect directly to the pin of each output choke, use 10 mil differencial pair, and 20 mil gap to other phase pair. Less via as possible. 2. Switching ripple current path: a. Input capacitor to high side MOSFET. b. Low side MOSFET to output capacitor. c. The return path of input and output capacitor. d. Separate the power and signal GND. e. The switching nodes (the connection node of high/low side MOSFET and inductor) is the most noisy points.Keep them away from sensitive small-signal node. f . Reduce parasitic R, L by minimum length, enough copper thickness and avoiding of via. 3. MOSFET driver should be closed to MOSFET.
SW1
L1
VIN RIN CIN
VOUT
COUT
RL
V
L2 SW2
Figure 22. Power Stage Ripple Current Path
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RT8800/B
Next to IC +12V 0.1uF VCC BST DRVH IN SW CBOOT LO1 CIN +12V or +5V PWM RT GND RICOM ICOMMON FB RFB Locate near MOSFETs CSPx GND PI RDRD COMP CC RC Locate next to FB Pin VCC CBP Next to IC +5VIN
VCORE
COUT
RT8800/B
RT9603
DRVL GND
Figure 23. Layout Consideration
Figure 24
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RT8800/B
Figure 25
Figure 26
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RT8800/B
Figure 27
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RT8800/B
Outline Dimension
D
D2
SEE DETAIL A L
1
E
E2
1
1 2
e A A1 A3
b
2
DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated.
Symbol A A1 A3 b D D2 E E2 e L
Dimensions In Millimeters Min 0.800 0.000 0.175 0.180 2.950 1.300 2.950 1.300 0.500 0.350 0.450 Max 1.000 0.050 0.250 0.300 3.050 1.750 3.050 1.750
Dimensions In Inches Min 0.031 0.000 0.007 0.007 0.116 0.051 0.116 0.051 0.020 0.014 0.018 Max 0.039 0.002 0.010 0.012 0.120 0.069 0.120 0.069
V-Type 16L QFN 3x3 Package
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RT8800/B
A
H M
J
B
F
C I D
Symbol A B C D F H I J M
Dimensions In Millimeters Min 9.804 3.810 1.346 0.330 1.194 0.178 0.102 5.791 0.406 Max 10.008 3.988 1.753 0.508 1.346 0.254 0.254 6.198 1.270
Dimensions In Inches Min 0.386 0.150 0.053 0.013 0.047 0.007 0.004 0.228 0.016 Max 0.394 0.157 0.069 0.020 0.053 0.010 0.010 0.244 0.050
16- Lead SOP Plastic Package
Richtek Technology Corporation
Headquarter 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611
Richtek Technology Corporation
Taipei Office (Marketing) 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com
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